The Reason for the Leakage Current of MOS Tube

The cause of the MOS  tube's leakage current

Power dissipation is caused by leakage current, especially at lower threshold voltages. Learn about the six different causes of leakage currents in MOS transistors.

1. Reverse bias - leakage current at the PN junction

2. Leakage current below the threshold

3. Reduction of the barrier due to drainage

4. Vth roll-off

5. The impact of the working environment's temperature

6. Leakage current tunneling into and through gate oxide

7. Current leakage from the substrate to the gate oxide layer due to hot carrier injection

8. Current leakage owing to drain decrease generated by the gate (GIDL)

Before continuing, make sure you understand the fundamental concepts of MOS transistors, as this will help you understand what follows.

1. Reverse Biased pn Junction Leakage Current

During transistor operation, MOS  transistor s' drain/source and substrate junctions are reverse biased. As a result, the device's leakage current is reverse biased. This leakage current could be caused by minority carrier drift/diffusion in the reverse biased region, as well as the avalanche effect's creation of electron-hole pairs. The reverse bias leakage current at a pn junction is determined by the doping concentration and junction area.

The band-to-band tunneling (BTBT) effect dominates the reverse bias leakage current in strongly doped pn junctions in the drain/source and substrate regions. Electrons tunnel straight from the p-valence region's band to the n-conduction region's band in interband tunneling. For electric fields greater than 10 6 V/cm, BTBT  is evident.

Figure 1. Band-to-Band Tunneling in a Reverse-Biased PN Junction of a MOS Transistor

It's worth noting that in the context of this research, we define tunneling as occurring even when the electron's energy is substantially lower than the barrier.

2. Subthreshold leakage current

The transistor is considered to be biased in the subthreshold or weak inversion zone when the gate voltage is less than the threshold value (V th) but larger than zero. The concentration of minority carriers is small, but not zero, in weak inversion.  The entire voltage drop occurs at the drain-substrate pn junction in this scenario for |VDS| typical values > 0.1V.

The electric field component parallel to the Si-SiO contact between drain and source is minimal. The drift current is low because to the small electric field, and the subthreshold current is mostly diffusion current.

Drainage Induced Barrier Lowering (DIBL)

Drain induced barrier lowering, or DIBL, is the primary cause of subthreshold leakage current. The depletion zones of the drain and source interact in short-channel devices to lower the source barrier. Subthreshold leakage currents originate from the source injecting charge carriers into the channel surface.

DIBL is evident in high drain voltage and short channel devices.

V th roll off

The threshold voltage of MOS  devices falls as channel length decreases. V th roll-off is the name given to this phenomena (or threshold voltage roll-off). The drain and source depletion areas in short-channel devices extend further into the channel length, draining a portion of the channel.

As a result, inverting the channel requires a lower gate voltage, lowering the threshold voltage. This effect is more noticeable at higher drain voltages. Because subthreshold current is inversely related to threshold voltage, lowering the threshold voltage increases subthreshold leakage current.

The effect of operating temperature

Leakage current is also affected by temperature. The threshold voltage falls as the temperature rises. In other words, as the temperature rises, the subthreshold current rises as well.

3. Tunneling into and through the gate oxide leakage current

Thin gate oxides provide large electric fields on the SiO layer in short-channel devices. Electrons tunnel from the substrate to the gate and from the gate through the gate oxide to the substrate when the oxide thickness is low and the electric field is high, resulting in gate oxide tunneling current.

Consider the band diagram shown in the figure.

Figure 2. Band Diagram of a MOS Transistor with (a) Flat Band, (b) Positive Gate Voltage, and (c) Negative Gate Voltage

The first figure, Figure 2(a), is a flat-band MOS  transistor.  i.e. no charge exists in it.

The band diagram changes when the gate terminal is forward biased, as illustrated in the second graph, Figure 2. (b). Gate current is generated when electrons at the strongly inverted surface tunnel into or through the SiO layer.

A negative gate voltage, on the other hand, causes electrons from the n+ polysilicon gate to tunnel into or through the  SiO2  layer, producing in a gate current, as shown in Fig. 2. (c).

Fowler-Nordheim tunnel and direct tunnel

There are mainly two tunneling mechanisms between the gate and the substrate. they are:

Fowler-Nordheim tunneling, where electrons tunnel through a triangular barrier

Direct tunneling, where electrons tunnel through a ladder barrier

Figure 3. Band Diagrams Showing (a) Fowler-Nordheim Tunneling through a Triangular Barrier of Oxides and (b) a Ladder Barrier for Direct Tunneling through Oxides

You can see the band diagrams of the two tunneling mechanisms in Figures 3(a) and 3(b) above.

4. Leakage current due to hot carrier injection from the substrate to the gate oxide

The high electric field near the substrate-oxide interface excites electrons or holes, which pass the substrate-oxide interface and into the oxide layer in short-channel devices. Hot carrier injection is the term for this phenomenon.

Figure 4. Band Diagram Depicting Electrons Gaining Sufficient Energy due to High Electric Field to Cross the Oxide Barrier (Hot Carrier Injection Effect)

Electrons are more susceptible to this phenomena than holes. This is due to the fact that electrons have a lower effective mass and a lower barrier height than holes.

5. Leakage current due to gate induced drain drop (GIDL)

Take an NMOS transistor with a p-type substrate as an example. Positive charge builds exclusively at the oxide-substrate interface when there is a negative voltage at the gate terminal. Due to the holes accumulating on the substrate, the surface behaves as a more strongly doped p-region than the substrate.

As a result, the depletion zone along the drain-substrate contact is thinner near the surface (compared to the thickness of the depletion region in the bulk).

Figure 5. (a) Formation of a Thin Depletion Region Along the Surface at the Drain-Substrate Interface and (b) GIDL Current Flow due to Avalanche Effect and BTBT-Generated Carriers

Avalanche and interband tunneling effects (as discussed in the first part of this study) occur due to the thin depletion area and greater electric field. As a result, minority carriers are created in the drain region under the gate, and the negative gate voltage pushes them into the substrate. Leakage current rises as a result of this.

6. Leakage current due to punch-through effect

Because the drain and source are close together in short-channel devices, the depletion areas of the two terminals converge and eventually overlap. "Penetration" is said to have occurred in this case.

For most carriers from the source, the punch-through effect lowers the barrier. The number of carriers entering the substrate increases as a result of this. The drain collects some of these carriers, while the remainder generate leakage current.